The present invention relates to reducing a direct current (DC) bias during level shifting, and more particularly, to an apparatus for performing level shift control in an electronic device.
A conventional level shift circuit may suffer from some problems corresponding to the architecture thereof, such as a low speed problem due to large parasitic capacitance of some high voltage device, and another problem due to the high swing level of the upper side thereof. For example, the propagation delay may reach five nanoseconds (ns), which may degrade the overall performance of the conventional electronic device in which the conventional level shift circuit is installed. According to the related art, it is proposed to reduce the swing level by adding clamping circuits into this conventional level shift circuit. However, additional problems such as some side effects may be introduced. For example, adding the clamping circuits may cause huge quiescent, and may increase the DC bias, where the DC bias may approach zero before the clamping circuits are added.
Another conventional level shift circuit such as that in the U.S. Pat. No. 7,839,197 is proposed to improve the speed, and the clamping circuits may further be added into the other conventional level shift circuit as mentioned above when needed, but the current sources in the conventional current control circuit of the other conventional level shift circuit may cause large boot voltage leakage. As a result, the whole regulator implemented by using the other conventional level shift circuit may encounter an out of regulation problem when a light load is applied. Although the speed is improved, the DC bias is greatly increased. For example, the DC bias in the other conventional level shift circuit may reach ten microamperes (μA).
In conclusion, there are many problems in the conventional level shift circuits. Thus, a novel architecture is required to improve the speed with fewer side effects, in order to guarantee the overall performance of the whole system.